AI compute. Connectivity. Data processing. Storage.
Our silicon experts and design-agent system take customer chip projects from a product idea to a tested design, with Melten responsible for the engineering work.
AI infrastructure brings together demanding design problems. Explore each highlighted block to see its design focus and available engineering stories.
Design focus: data movement, protocol processing, and hardware offload. This domain illustrates data-processing design challenges within AI infrastructure. Project scope and validation evidence will be detailed in its engineering story.
Engineering story coming soonEach chip class calls for different architectures and verification strategies. The common thread is Melten’s design-agent system: agents and silicon experts working through design, verification, and implementation.
Translate the design goal into architecture, hardware–software boundaries, and RTL—with human direction at key decisions.
Agents designed a new accelerator architecture while reusing the PCIe and DDR platform from an earlier Melten controller project.
Cross-check implementations, diagnose failures, and iterate. Verification is part of the engineering process throughout.
When a byte-write fault blocked Host discovery, agents traced it on the board, repaired the logic, and added regression tests.
Connect claims to implementation and validation results. Each engineering story states what was built, measured, and verified.
Board measurements exposed a bottleneck in the vendor bridge. Agents implemented Melten’s own PCIe AXI bridge and validated it with NVMe traffic.
Explore FPGA implementations across AI compute, connectivity, and storage, with each project’s scope, measurements, and validation results documented.
Melten’s agents built a custom PCIe Gen4 x16 interface on an FPGA whose built-in controller stops at Gen3. An encrypted NVMe drive demonstrates 28.4 GB/s reads and Linux boot, with reusable interface, encryption, and search IP for future customer designs.
Directed by one designer, Melten’s design-agent system built an NVMe SSD front end on an AMD Versal FPGA. Over PCIe Gen4 x8 it moved 13.9 GB/s each way and 3.3 million 4 KiB I/Os per second.
Directed by one designer, Melten’s design-agent system built a three-port PCIe Gen4 switch on an AMD Versal FPGA. Two off-the-shelf NVMe SSDs ran through it at 87–99% of their rated speeds.
Melten’s design-agent system re-architected an FPGA NPU for Gemma 4 26B-A4B, routed experts, mixed attention, and 32K context—with 11,226 exact hardware/reference output checks.
Melten’s design-agent system took a human-set requirement through architecture, RTL, software, verification, implementation, lab bring-up, and independent closure in 122 hours.
Data movement and protocol-processing architectures.
ENGINEERING STORY COMING SOONTell us what you want your next chip to do.