An LLM accelerator,
built in five days.
Starting with a human-set requirement, Melten’s agent fleet took a new FPGA accelerator through architecture, RTL, software, verification, implementation, lab bring-up, and independent closure in 122 hours.4
- 122 hours
- Campaign start to independent closure of all six outcomes
- 7B
- Largest Qwen2.5 model verified on the board
- 3 models
- 0.5B, 1.5B, and 7B on one hardware image
- 24,456
- Hardware output steps matched the fixed-point reference
- 3.5B AI tokens
- Approximately $2,754 in model usage across the campaign
The result in brief
Requirements in. Verified hardware out.
The owner set the goal and approved key decisions. Agents produced the architecture, fixed-point model, RTL, host runtime, verification, FPGA image, and lab evidence.
One image, three model sizes.
Qwen2.5-0.5B, 1.5B, and 7B use the same matrix, attention, vector, and KV engines. Moving between them changes configuration and model layout, not the hardware design.
The toolchain was part of the test.
Post-synthesis verification exposed two FPGA-tool translation faults. The fleet isolated both and added netlist regressions around the repaired structures.
Performance came from the board.
Decode, prefill, DDR efficiency, timing, and utilization below were measured on or reported from the accepted XUP-P3R image—not projected from a future chip.
The gap between correct code
and working hardware.
Simulation, synthesis, routing, device software, memory behavior, and the physical board can each change the answer. Closing the loop means finding which layer broke—and proving the repair.
Many AI design tools accelerate one stage, then return the integration work to engineers. This campaign kept the entire loop inside the fleet: architecture, design, verification, FPGA builds, lab execution, measurement, and independent review.
RTL was right. Two synthesized structures were not.
Vivado 2026.1 translated exponent sign extension and a BRAM-backed lookup-table index differently from RTL behavior. Netlist checks localized the faults; the agents changed the implementation and made those checks permanent regressions.
The smallest format was not accepted blindly.
An all-INT8 7B candidate missed the frozen quality gate. The fleet retained INT16 only for the final language-model head, raising next-token agreement with the original model to 98.4% while keeping the rest group-scaled INT8.
One datapath,
three Qwen2.5 sizes.
Batch 1, greedy decoding, and four frozen prompts per model. Decode results are full-run averages through the campaign-qualified 2K context—not a short-window rate.
| Model | Decode | Prefill | DDR efficiency at 2K | Exact hardware/reference steps | Next-token agreement with original model |
|---|---|---|---|---|---|
| Qwen2.5-0.5B | 53.5 tok/s | 148.5 tok/s | 75.1% | 8,152 / 8,152 | 95.3% |
| Qwen2.5-1.5B | 18.8 tok/s | 45.7 tok/s | 82.0% | 8,152 / 8,152 | 97.7% |
| Qwen2.5-7B | 4.18 tok/s | 9.8 tok/s | 91.1% | 8,152 / 8,152 | 98.4% |
The performance and efficiency columns come from the accepted FPGA image. Exactness compares hardware token IDs and per-step logits digests with the independent fixed-point reference. The last column is a separate, pre-hardware quality test against the original full-precision model. Twelve board runs contributed 24,456 exact comparisons.3
DDR efficiency at the longest qualified context
Useful model bytes per completed token divided by saturated DDR read bandwidth on the same image. The frozen acceptance target was 60%.
Closed loops,
not a one-shot generation.
Targets were fixed before results. Failed checks triggered another design, build, or measurement cycle; accepted claims remained bound to their exact artifacts.
Architecture was part of the work.
The agents did not receive a completed microarchitecture. They derived the datapath, numerical contract, software/hardware boundary, observability, and recovery behavior from the campaign requirement.
Independent implementations cross-checked.
The hardware matched a bit-accurate fixed-point model. That model was separately quality-gated against a generalized floating-point host reference.
Every accepted result had an identity.
The campaign bound the board run to the exact image build ID, model revisions, layout digests, candidate commit, checkpoint, and independent closure record.
- Hour 0Campaign startedCross-model plan review closed 26 minutes later.
- Hour 9A full model layer matched exactlyRTL simulation against the fixed-point reference.
- Hour 53First complete image met timingThe PCIe, DDR, and accelerator design was fully routed.
- Hour 67First lab-board runHardware bring-up moved verification onto the device.
- Hour 87First complete model verifiedQwen2.5-0.5B completed all frozen runs.
- Hour 1091.5B model verifiedThe same hardware image advanced to the next model size.
- Hour 1137B model verifiedThe largest model completed on that image.
- Hour 122All six outcomes closedIndependent review accepted the final evidence.
Human direction stayed where it mattered.
The project owner set the requirement, approved the plan and model authorities, and authorized lab access. The agent fleet performed the detailed architecture, implementation, verification, build, bring-up, diagnosis, and evidence assembly. It also reused the PCIe and DDR platform from an earlier Melten controller campaign—a concrete example of design knowledge compounding across projects.
Under the hood.
A host-attached, batch-1 FPGA prototype designed to turn available memory bandwidth into completion-visible inference.
- Hardware
- BittWare XUP-P3R with an AMD Virtex UltraScale+ VU9P, timing-closed at 200 MHz.
- Implementation
- 34.6% of LUTs, 18.1% of registers, 27.8% of DSPs, 27.1% of BRAM, and 17.2% of URAM.
- Memory
- Four DDR4 channels measured at 35.284 GB/s aggregate sustained reads on the accepted image.
- Numerics
- Group-64 INT8 weights with 16-bit integer activations; the 7B language-model head remains INT16.
- Execution
- Host-directed PCIe/BAR/DMA command flow; no soft processor in the device command or compute path.
- Context
- The model ladder supports at least 32K positions. This campaign qualified prompt-plus-generated runs through 2,048 tokens.
How N10 compares.
Architect Labs’ Redwood Nano is the closest published comparison: another AI-designed accelerator deployed on an FPGA for transformer inference.1
| Measure | Melten N10 | Architect Labs Redwood Nano |
|---|---|---|
| Language models demonstrated on hardware | Qwen2.5 0.5B, 1.5B, and 7B | Qwen3-0.6B |
| Largest model with measured hardware results | 7B parameters | 0.6B parameters |
| Published short-context result on a roughly 0.5B model | 57.8 tokens per second | 12.1 tokens per second |
| Share of measured board memory bandwidth used2 | 84–95% across three model sizes | ~54% |
| Correctness evidence | On hardware: all 24,456 output steps matched the fixed-point reference across three models and 2,048-token sequences. Corrupted data and malformed commands were also caught.Before hardware: every block was checked in simulation against the same reference. | On hardware: the preprint reports 128-token performance, but not output-accuracy results.Before hardware: 95% test coverage and formal checks. |
| Plan to model running on hardware | Under 5 days 7B; first model in under 4 days | About 3 weeks 2 weeks to design, 1 week to bring up the model |
| Human role | One owner set goals and approved decisions | Two architects wrote the specification |
| Basis of headline results | Measured on the FPGA board | FPGA measurements; chip-level gains projected to an 8 nm process |
| Design approach | Purpose-built LLM engine; model size set at load time | Programmable tiles with RISC-V control cores |
These are different prototypes on different FPGA boards. N10’s board has about 3.2× more theoretical memory bandwidth (51.2 versus 16 GB/s), so raw token rates are not a like-for-like comparison. The normalized chart below asks a narrower question: how much of each board’s own measured memory bandwidth did the design turn into useful work? Redwood is a programmable architecture aimed at low-power edge devices; N10 is purpose-built for Qwen2.5 inference.
Share of each board’s measured memory bandwidth put to work
Short context, approximately 128 tokens. Higher is better. N10’s acceptance target was 60%. This diagnostic window is shown only to match Redwood’s published measurement window; the primary N10 results above are full-run averages through 2K.
View chart data and calculation inputs
| Design and model | Share of measured bandwidth | Tokens/s | Bytes read per token |
|---|---|---|---|
| Melten N10 · Qwen2.5-0.5B | 83.7% | 57.8 | 511 MB |
| Melten N10 · Qwen2.5-1.5B | 90.9% | 20.1 | 1.60 GB |
| Melten N10 · Qwen2.5-7B | 95.5% | 4.3 | 7.83 GB |
| Architect Labs Redwood Nano · Qwen3-0.6B | 54.0% | 12.1 | 0.63 GB |
The same closed loop,
pointed at larger targets.
N10 is an FPGA prototype: real hardware evidence for the architecture and design process, before an ASIC implementation.
- Architect Labs, “Redwood: A Frontier AI Accelerator Designed, Verified, and Deployed from Scratch in 2 Weeks by AI,” arXiv:2608.26418 (preprint, August 2026), Table I and Section IV; and Architect Labs’ Redwood article. Redwood Nano runs on an AMD Versal VPK180 at 250 MHz with LPDDR4.
- Share of measured memory bandwidth = tokens per second × bytes read per token ÷ sustained bandwidth measured on the same board. N10 uses a 35.3 GB/s saturated-read benchmark from the same hardware image and lab session at short context; through 2,048 tokens, the corresponding share is 75–91%. Redwood uses 12.1 tokens/s × 0.627 GB per token ÷ 14.04 GB/s sustained bandwidth, all from Section IV-A of its preprint.
- Four fixed prompts per model were decoded greedily to 2,048 tokens. For correctness, every step’s token ID and a digest of all output logits were compared with a bit-accurate software model of the design’s integer arithmetic. Quality was measured separately: top-1 agreement between that model and the original full-precision model on a fixed, long-context set of 256 scored positions, against bounds fixed before measurement. Most disagreements were near-ties between the original model’s top two candidates. N10 is an FPGA prototype; no ASIC power or area claims are made.
- Elapsed time is counted from project start on September 29, 2026 at 09:49 UTC to independent closure of all six outcomes on October 4 at 11:25 UTC. The cross-model plan review closed 26 minutes after project start; the 7B model was verified on the board at hour 113. The work reused the PCIe and DDR4 platform from an earlier Melten controller campaign and the full-precision Qwen2.5 reference and quality tests from an earlier NPU program. The accelerator architecture itself was new.